System Control Module (SCM)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
13-14
Freescale Semiconductor
— Provide read/write/execute access rights, supervisor/user privilege levels.
— One single register (GPACR0) controls access to 14 of the on-chip peripheral modules.
— One register (GPACR1) controls access for IPS reads and writes to the flash module.
— Reset state provides supervisor-only read/write access to each of these peripheral spaces.
13.7.3
Memory Map/Register Definition
The memory map for the SACU program-visible registers within the system control module (SCM) is
shown in
. The MPR, PACR, and GPACRs are 8 bits wide.
13.7.3.1
Master Privilege Register (MPR)
The MPR specifies the access privilege level associated with each bus master in the platform. The register
provides one bit per bus master, where bit 3 corresponds to master 3 (Fast Ethernet controller), bit 2 to
master 2 (DMA Controller), and bit 0 to master 0 (ColdFire core).
Table 13-7. SACU Register Memory Map
IPSBAR
Offset
[31:28]
[27:24]
[23:20]
[19:16]
[15:12]
[11:8]
[7:4]
[3:0]
0x020
MPR
PPMRS
PPMRC
IPSBMT
0x024
PACR0
PACR1
PACR2
PACR3
0x028
PACR4
PACR5
PACR6
PACR7
0x02C
PACR8
PACR9
—
—
0x030
GPACR0
GPACR1
—
—
0x034
—
—
—
—
0x038
—
—
—
—
0x03C
—
—
—
—
IPSBAR
Offset: 0x0020 (MPR)
Access: read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
MPR
W
Reset:
0
0
0
0
0
0
1
1
Figure 13-8. Master Privilege Register (MPR)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
