General Purpose Timer Module (GPT)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
23-19
NOTE
The PAI input and GPT channel 3 use the same pin. To use the PAI input,
disconnect it from the output logic by clearing the channel 3 output mode
(OM3) and output level (OL3) bits. Also clear the channel 3 output compare
mask bit (OC3M3).
The PA counter register (GPTPACNT) reflects the number of pulses from the divide-by-64 clock since the
last reset.
NOTE
The GPT prescaler generates the divide-by-64 clock. If the timer is not
active, there is no divide-by-64 clock.
Figure 23-22. Channel 3 Output Compare/Pulse Accumulator Logic
23.7.7
General-Purpose I/O Ports
An I/O pin used by the timer defaults to general-purpose I/O unless an internal function that uses that pin
is enabled.
The PORTT
n
pins can be configured for an input capture function or an output compare function. The
IOS
n
bits in the GPT IC/OC select register configure the PORTT
n
pins as input capture or output compare
pins.
The PORTT
n
data direction register controls the data direction of an input capture pin. External pin
conditions trigger input captures on input capture pins configured as inputs.
To configure a pin for input capture:
1. Clear the pin’s IOS bit in GPTIOS.
2. Clear the pin’s DDR bit in PORTT
n
DDR.
3. Write to GPTCTL2 to select the input edge to detect.
PORTT
n
DDR does not affect the data direction of an output compare pin. The output compare function
overrides the data direction register but does not affect the state of the data direction register.
To configure a pin for output compare:
1. Set the pin’s IOS bit in GPTIOS.
2. Write the output compare value to GPTC
n
.
PAD
OM3
OL3
CHANNEL 3 OUTPUT COMPARE
PULSE
ACCUMULATOR
OC3M3
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
