Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
18-24
Freescale Semiconductor
18.5.4.2
Interrupt Mask Register (EIMR)
The EIMR register controls which interrupt events are allowed to generate actual interrupts. All
implemented bits in this CSR are read/write. This register is cleared upon a hardware reset. If the
corresponding bits in the EIR and EIMR registers are set, the interrupt is signalled to the CPU. The
interrupt signal remains asserted until a 1 is written to the EIR bit (write 1 to clear) or a 0 is written to the
EIMR bit.
IPSBAR
Offset: 0x1008 (EIMR)
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R HBER
R
BABR BABT GRA
TXF
TXB
RXF
RXB
MII
EBER
R
LC
RL
UN
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 18-5. Interrupt Mask
Register (EIMR)
Table 18-13. EIMR Field Descriptions
Field
Description
31–19
(see
for the
corresponding bit names)
Interrupt mask. Each bit corresponds to an interrupt source defined by the EIR register. The
corresponding EIMR bit determines whether an interrupt condition can generate an interrupt. At
every processor clock, the EIR samples the signal generated by the interrupting source. The
corresponding EIR bit reflects the state of the interrupt signal even if the corresponding EIMR bit
is set.
0 The corresponding interrupt source (see
) is masked.
1 The corresponding interrupt source (see
) is not masked.
18–0
Reserved, should be cleared.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
