General Purpose Timer Module (GPT)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
23-11
23.6.11 GPT System Control Register 2 (GPTSCR2)
IPSBAR
Offset: 0x1A_000D (GPTSCR2)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
TOI
0
PUPT
RDPT
TCRE
PR
W
Reset:
0
0
0
0
0
0
0
0
Figure 23-13. GPT System Control Register 2 (GPTSCR2)
Table 23-14. GPTSCR2 Field Descriptions
Field
Description
7
TOI
Enables timer overflow interrupt requests.
1 Overflow interrupt requests enabled
0 Overflow interrupt requests disabled
6
Reserved, should be cleared.
5
PUPT
Enables pull-up resistors on the GPT ports when the ports are configured as inputs.
1 Pull-up resistors enabled
0 Pull-up resistors disabled
4
RDPT
GPT drive reduction. Reduces the output driver size.
1 Output drive reduction enabled
0 Output drive reduction disabled
3
TCRE
Enables a counter reset after a channel 3 compare.
1 Counter reset enabled
0 Counter reset disabled
Note: When the GPT channel 3 registers contain 0x0000 and TCRE is set, the GPT counter registers remain at
0x0000 all the time. When the GPT channel 3 registers contain 0xFFFF and TCRE is set, TOF does not get
set even though the GPT counter registers go from 0xFFFF to 0x0000.
2–0
PR
Prescaler bits. Select the prescaler divisor for the GPT counter.
000 Prescaler divisor 1
001 Prescaler divisor 2
010 Prescaler divisor 4
011 Prescaler divisor 8
100 Prescaler divisor 16
101 Prescaler divisor 32
110 Prescaler divisor 64
111 Prescaler divisor 128
Note: The newly selected prescaled clock does not take effect until the next synchronized edge of the prescaled
clock when the clock count transitions to 0x0000.)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
