Freescale Semiconductor
27-1
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Chapter 27
I
2
C Interface
27.1
Introduction
This chapter describes the I
2
C module, clock synchronization, and I
2
C programming model registers. It
also provides extensive programming examples.
27.1.1
Block Diagram
is a I
2
C module block diagram, illustrating the interaction of the registers described in
Section 27.2, “Memory Map/Register Definition”.
Figure 27-1. I
2
C Module Block Diagram
Address
Compare
In/Out
Data
Shift
Start, Stop,
Input
Sync
Clock
Control
Registers and Slave Interface
Address Decode
I
2
C Address
Data MUX
Address
IRQ
Data
and
Arbitration
Control
Register
Internal Bus
Register
I
2
C Frequency
Divider Register
I
2
C Data
I/O Register
I
2
C Status
Register
I
2
C Control
Register
I2C_SCL
I2C_SDA
(I2FDR)
(I2CR)
(I2SR)
(I2DR)
(I2ADR)
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
