General Purpose Timer Module (GPT)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
23-5
23.6.1
GPT Input Capture/Output Compare Select Register (GPTIOS)
23.6.2
GPT Compare Force Register (GPCFORC)
0x1A_001E
GPT Port Data Direction Register (GPTDDR)
8
R/W
0x00
0x1A_001F
GPT Test Register (GPTTST)
8
1
Addresses not assigned to a register and undefined register bits are reserved for expansion.
2
This register is 16 bits wide, and should be read using only word accesses.
IPSBAR
Offset: 0x1A_0000 (GPTIOS)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
IOS
W
Reset:
0
0
0
0
0
0
0
0
Figure 23-2. GPT Input Capture/Output Compare Select Register (GPTIOS)
Table 23-4. GPTIOS Field Descriptions
Field
Description
7–4
Reserved, should be cleared.
3–0
IOS
I/O select. The IOS[3:0] bits enable input capture or output compare operation for the corresponding timer channels.
These bits are read anytime (always read 0x00), write anytime.
1 Output compare enabled
0 Input capture enabled
IPSBAR
Offset: 0x1A_0001 (GPCFORC)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
0
0
0
0
FOC
W
Reset:
0
0
0
0
0
0
0
0
Figure 23-3. GPT Input Compare Force Register (GPCFORC)
Table 23-3. QSPI Memory Map (continued)
IPSBAR
Offset
1
Register
Width
(bits)
Access
Reset Value
Section/Page
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
