Pulse-Width Modulation (PWM) Module
Freescale Semiconductor
29-20
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Eqn. 29-10
29.3.2.6.1
Center-Aligned Output Example
As an example of a center-aligned output, consider the following case:
Clock source = internal bus clock, where internal bus clock = 40 MHz (25 ns period)
PPOL
n
= 0, PWMPER
n
= 4, PWMDTY
n
= 1
PWM
n
frequency = 40 MHz / (2
×
4) = 5 MHz
PWM
n
period = 200 ns
Shown below is the generated output waveform.
Figure 29-19. PWM Center-Aligned Output Example Waveform
29.3.2.7
PWM 16-Bit Functions
The PWM timer also has the option of generating eight 8-bit channels or four 16-bit channels for greater
PWM resolution. This 16-bit channel option is achieved through the concatenation of two 8-bit channels.
The PWMCTL register contains four concatenation control bits, each used to concatenate a pair of PWM
channels into one 16-bit channel. Channels 0 and 1 are concatenated with the CON01 bit, channels 2 and
3 are concatenated with the CON23 bit, and so on. Change these bits only when both corresponding
channels are disabled.
, when channels 2 and 3 are concatenated, channel 2 registers become the high
order bytes of the double byte channel. When channels 0 and 1 are concatenated, channel 0 registers
become the high order bytes of the double byte channel.
When using the 16-bit concatenated mode, the clock source is determined by the low order 8-bit channel
clock select control bits (the odd numbered channel). The resulting PWM is output to the pins of the
corresponding low order 8-bit channel, as shown in
. The polarity of the resulting PWM
output is controlled by the PPOL
n
bit of the corresponding low order 8-bit channel as well.
After concatenated mode is enabled (PWMCTL[CON
nn
] bits set), enabling/disabling the corresponding
16-bit PWM channel is controlled by the low order PWME
n
bit. In this case, the high order bytes’ PWME
n
bits have no effect, and their corresponding PWM output is disabled.
In concatenated mode, writes to the 16-bit counter by using a 16-bit access or writes to the low or high
order byte of the counter resets the 16-bit counter. Reads of the 16-bit counter must be made by 16-bit
access to maintain data coherency.
Duty Cycle
1
PWMPOL PPOL
n
[
]
PWMDTY
n
PWMPER
n
-------------------------------
–
–
⎝
⎠
⎛
⎞
100%
×
=
PWMn Duty Cycle
1
1
4
---
–
⎝
⎠
⎛
⎞
100% 75%
=
×
=
DUTY CYCLE = 75%
E = 25ns
PERIOD = 200ns
E = 25ns
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
