Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
18-37
18.5.4.14 Descriptor Individual Upper Address Register (IAUR)
The IAUR is written by the user. This register contains the upper 32 bits of the 64-bit individual address
hash table used in the address recognition process to check for possible match with the DA field of receive
frames with an individual DA. This register is not reset and must be initialized by the user.
IPSBAR
Offset: 0x1118 (IAUR)
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
IADDR1
W
Reset
Undefined
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
IADDR1
W
Reset
Undefined
Figure 18-17. Descriptor Individual Upper Address Register (IAUR)
Table 18-26. IAUR Field Descriptions
Field
Description
31–0
IADDR1
The upper 32 bits of the 64-bit hash table used in the address recognition process for receive
frames with a unicast address. Bit 31 of IADDR1 contains hash index bit 63. Bit 0 of IADDR1
contains hash index bit 32.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
