Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
18-30
Freescale Semiconductor
The MII_SPEED field must be programmed with a value to provide an EMDC frequency of less than or
equal to 2.5 MHz to be compliant with the IEEE 802.3 MII specification. The MII_SPEED must be set to
a non-zero value to source a read or write management frame. After the management frame is complete
the MSCR register may optionally be set to zero to turn off the EMDC. The EMDC generated has a 50%
duty cycle except when MII_SPEED is changed during operation (change takes effect following a rising
or falling edge of EMDC).
If the system clock is 25 MHz, programming this register to 0x0000_0005 results in an EMDC frequency
of 25 MHz
×
1/ (5
×
2) = 2.5 MHz. A table showing optimum values for MII_SPEED as a function of
system clock frequency is provided below.
18.5.4.8
MIB Control Register (MIBC)
The MIBC is a read/write register used to provide control of and to observe the state of the MIB block.
This register is accessed by user software if there is a need to disable the MIB block operation. For
example, to clear all MIB counters in RAM the user should disable the MIB block, then clear all the MIB
RAM locations, then enable the MIB block. The MIB_DISABLE bit is reset to 1. See
locations of the MIB counters.
Figure 18-10. MII Speed Control Register (MSCR)
Table 18-18. MSCR Field Descriptions
Field
Description
31–8
Reserved, should be cleared.
7
DIS_PREAMBLE
Asserting this bit causes preamble (32 1’s) not to be prefixed to the MII management frame. The MII
standard allows the preamble to be dropped if the attached PHY device(s) does not require it.
6–1
MII_SPEED
MII_SPEED controls the frequency of the MII management interface clock (EMDC) relative to the
system clock. A value of 0 in this field turns off the EMDC and leave it in low voltage state. Any
non-zero value results in the EMDC frequency of 1/(MII_SPEED
×
2) of the system clock frequency.
0
Reserved, should be cleared.
Table 18-19. Programming Examples for MSCR
System Clock Frequency
MII_SPEED (field in reg)
EMDC frequency
25 MHz
0x5
2.5 MHz
33 MHz
0x7
2.36 MHz
40 MHz
0x8
2.5 MHz
50 MHz
0xA
2.5 MHz
60 MHz
0xD
2.5 MHz
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
