Revision History
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
B-7
Freescale Semiconductor
Table 2-1 / Section 2.2
• Set table caption to repeat on every page.
• Changed footnote 11 to “VDD1, VDD2, VDDPLL and PHY_VDD pins are for decoupling only,
and should NOT have power directly applied to them." and corrected references so that only
pins VDDPLL, PHY_VDDA, PHY_VDDRX, PHY_VDDTX, and VDD reference this footnote.
• Corrected pin numbers as follows:
QSPI_CS0, 80 LQFP package: should be 28 instead of 58
FlexCAN SYNCA, 112 LQFP package: should be 28 instead of —
FlexCAN SYNCA, 80 LQFP package: should be 20 instead of —
FlexCAN SYNCB, 112 LQFP package: should be 27 instead of —
FlexCAN SYNCB, 80 LQFP package: should be 19 instead of —
VSSX, 121MAPBGA package: should be — instead of an empty cell
Section 3.2.11 / Page 3-8
Added cross-reference to FLASHBAR register.
Chapter 6
• Added register and bit acronyms.
• Removed references to FIFO-based functionality for RNGOUT.
• Formatted register figures and descriptions in accordance with manual conventions.
Chapter 7
Replaced “Low-Power Divider Register (LPDR)” with “Low-Power Control Register (LPCR)” and
corrected its address to match the rest of the document.
Chapter 8
Replaced all register addresses with correct values and updated several register names.
Table 8-1 / Page 8-3
Corrected register names in memory map table - changed RCCTL to RTCCTL, DAYS to DAYR,
ALARM_DAY to DAY_ALARM.
Section 8.2.1 / Page 8-3
Updated explanation of reset condition (POR resets RTC) in HOURMIN and SECONDS register
descriptions
Section 8.2.1.5 / Page 8-7
Deleted extraneous XTL bit description in RTCCTL register description.
Section 8.3.3 / Page 8-12
Deleted extraneous sentence “For example, to turn off the LCD controller...” in Minute Stopwatch
description.
Section 11.1.1 / Page 11-1
Corrected SRAM size.
Chapter 14
• Corrected register addresses to include proper offset (0x10_....).
• Updated register figures to SRS standards.
• Corrected register figure titles and added field description tables.
• In section 14.6.5, changed “If multiple pins are configured for the one function, then the rsult
is undefined” to “Some signals can be assigned to different pins (see Table 2-1). However, a
signal should not be assigned to more than one pin at the same time. If a signal is assigned
to two or more pins simultaneously, the result is undefined.”
Figure 14-1 / Page 14-2
Revised signal names to match the names in Chapter 2.
Section 15.1 / Page 15-2
Added cross-reference to exception vector assignments table in the ColdFire Core chapter.
Section 15.1.1.3 / Page 15-3 Updated exception vector mapping instructions and added cross-reference to exception vector
assignments table in the ColdFire Core chapter.
Table 15-2 / Page 15-4
• Changed the first interrupt controller number from INTC to INTC0.
• Added abbreviation ICBA (Interrupt Controller Base Address) to base address column.
Table 15-3 / Page 15-5
• Replaced references to IPSBAR with proper reference to ICBA in module offset column.
• Added n to appropriate register names.
Figure 15-2 / Page 15-6
• Changed register name from IPSBMT to IPRLn.
• Changed field label from INT[16:1] to INT[15:1].
Figure 15-4 / Page 15-8
Changed field label from INT_MASK[16:1] to INT_MASK[15:1].
Table 5. MCF52235RM Rev. 1 to Rev. 2 Changes (continued)
Location in Rev. 1
Description
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
