Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
31-25
Command Sequence:
Figure 31-20.
WAREG
/
WDREG
Command Sequence
Operand Data:
Longword data is written into the specified address or data register. The data is
supplied most-significant word first.
Result Data:
Command complete status is indicated by returning 0xFFFF (with S cleared)
when the register write is complete.
31.4.1.5.3
Read Memory Location (
READ
)
Read data at the longword address. Address space is defined by BAAR[TT,TM]. Hardware forces
low-order address bits to 0s for word and longword accesses to ensure that word addresses are
word-aligned and longword addresses are longword-aligned.
Command/Result Formats:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0x2
0x0
0x8
A/D
Register
D[31:16]
D[15:0]
Figure 31-19.
WAREG
/
WDREG
Command Format
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Byte
Command
0x1
0x9
0x0
0x0
A[31:16]
A[15:0]
Result
X
X
X
X
X
X
X
X
D[7:0]
Word
Command
0x1
0x9
0x4
0x0
A[31:16]
A[15:0]
Result
D[15:0]
Longword Command
0x1
0x9
0x8
0x0
A[31:16]
A[15:0]
Result
D[31:16]
D[15:0]
Figure 31-21.
READ
Command/Result Formats
WAREG/WDREG
???
LS DATA
’NOT READY’
NEXT CMD
’NOT READY’
XXX
BERR
MS DATA
’NOT READY’
NEXT CMD
’CMD COMPLETE’
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Trade
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prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
