ColdFire Core
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
3-9
A more detailed view of the hardware structure within the two pipelines is presented in
below. In these diagrams, the internal structure of the instruction fetch and operand execution
pipelines is shown:
Figure 3-9. Version 2 ColdFire Processor Instruction Fetch Pipeline Diagram
Figure 3-10. Version 2 ColdFire Processor Operand Execution Pipeline Diagram
The instruction fetch pipeline prefetches instructions from local memory using a two-stage structure. For
sequential prefetches, the next instruction address is generated by adding four to the last prefetch address.
This function is performed during the IAG stage and the resulting prefetch address gated onto the core bus
(if there are no pending operand memory accesses assigned a higher priority). After the prefetch address
is driven onto the core bus, the instruction fetch cycle accesses the appropriate local memory and returns
the instruction read data back to the IFP during the cycle. If the accessed data is not present in a local
memory (e.g., an instruction cache miss, or an external access cycle is required), the IFP is stalled in the
IAG
IC
IB
Core Bus
Address
Core Bus
Read Data
Opword
Extension 1
Extension 2
FIFO
IB
+4
DSOC
AGEX
Opword
Extension 1
Extension 2
Core Bus
Read Data
Core Bus
Address
Core Bus
Write Data
RGF
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of
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from
the
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International
Trade
Commission,
BGA-packaged
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sale
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States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
