Pulse-Width Modulation (PWM) Module
Freescale Semiconductor
29-6
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
29.2.5
PWM Center Align Enable Register (PWMCAE)
The PWMCAE register contains eight control bits for the selection of center-aligned outputs or
left-aligned outputs for each PWM channel. Write these bits only when the corresponding channel is
disabled. See
Section 29.3.2.5, “Left-Aligned Outputs”
and
Section 29.3.2.6, “Center-Aligned Outputs”
for a more detailed description of the PWM output modes.
Table 29-5. PWMPRCLK Field Descriptions
Field
Description
7
Reserved, must be cleared.
6–4
PCKB
Clock B prescaler select. These three bits control the rate of Clock B, which can be used for PWM channels2, 3, 6
and 7.
3
Reserved, must be cleared.
2–0
PCKA
Clock A prescaler select. These three bits control the rate of Clock A, which can be used for PWM channels0, 1, 4
and 5.
IPSBAR
Offset:
0x1B_0004 (PWMCAE)
Access:
SupervisorRead/Write
7
6
5
4
3
2
1
0
R
CAE7
CAE6
CAE5
CAE4
CAE3
CAE2
CAE1
CAE0
W
Reset:
0
0
0
0
0
0
0
0
Figure 29-6. PWM Center Align Enable Register (PWMCAE)
PCKB Clock
B
Rate
000
Internal bus clock
÷
2
0
001
Internal bus clock
÷
2
1
...
...
111
Internal bus clock
÷
2
7
PCKA
Clock A Rate
000
Internal bus clock
÷
2
0
001
Internal bus clock
÷
2
1
...
...
111
Internal bus clock
÷
2
7
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
