General Purpose Timer Module (GPT)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
23-8
Freescale Semiconductor
23.6.6
GPT System Control Register 1 (GPTSCR1)
Figure 23-8. Fast Clear Flag Logic
IPSBAR
Offset: 0x1A_0006 (GPTSCR1)
Access: Supervisor read/write
7
6
5
4
3
2
1
0
R
GPTEN
0
TFFCA
0
0
0
0
W
Reset:
0
0
0
0
0
0
0
0
Figure 23-7. GPT System Control Register 1 (GPTSCR1)
Table 23-9. GPTSCR1 Field Descriptions
Field
Description
7
GPTEN
Enables the general purpose timer. When the timer is disabled, only the registers are accessible. Clearing GPTEN
reduces power consumption. These bits are read anytime, write anytime.
1 GPT enabled
0 GPT and GPT counter disabled
6–5
Reserved, should be cleared.
4
TFFCA
Timer fast flag clear all. Enables fast clearing of the main timer interrupt flag registers (GPTFLG1 and GPTFLG2)
and the PA flag register (GPTPAFLG). TFFCA eliminates the software overhead of a separate clear sequence. See
.
When TFFCA is set:
• An input capture read or a write to an output compare channel clears the corresponding channel flag, CxF.
• Any access of the GPT count registers (GPTCNTH/L) clears the TOF flag.
• Any access of the PA counter registers (GPTPACNT) clears the PAOVF and PAIF flags in GPTPAFLG.
Writing logic 1s to the flags clears them only when TFFCA is clear.
1 Fast flag clearing
0 Normal flag clearing
3–0
Reserved, should be cleared.
Clear
Write GPTCn Registers
Read GPTCn Registers
TFFCA
Data Bit n
Write GPTFLG1 Register
CnF
CnF Flag
Because
of
an
order
from
the
United
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International
Trade
Commission,
BGA-packaged
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sale
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prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
