Fast Ethernet Controller (FEC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
18-42
Freescale Semiconductor
18.5.4.19 FIFO Receive Bound Register (FRBR)
The FRBR is an 8-bit register that the user can read to determine the upper address bound of the FIFO
RAM. Drivers can use this value, along with the FRSR to appropriately divide the available FIFO RAM
between the transmit and receive data paths.
IPSBAR
Offset: 0x114C (FRBR)
Access: User read/write
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
R_BOUND
0
0
W
Reset
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
Figure 18-22. FIFO Receive Bound Register (FRBR)
Table 18-31. FRBR Field Descriptions
Field
Description
31–10
Reserved, read as 0 (except bit 10, which is read as 1).
9–2
R_BOUND
Read-only. Highest valid FIFO RAM address.
1–0
Reserved, should be cleared.
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
