Enhanced Multiply-Accumulate Unit (EMAC)
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
4-3
4.2
Memory Map/Register Definition
The following table and sections explain the MAC registers:
4.2.1
MAC Status Register (MACSR)
The MAC status register (MACSR) contains a 4-bit operational mode field and condition flags.
Operational mode bits control whether operands are signed or unsigned and whether they are treated as
integers or fractions. These bits also control the overflow/saturation mode and the way in which rounding
is performed. Negative, zero, and multiple overflow condition flags are also provided.
Table 4-1. EMAC Memory Map
Register
Width
(bits)
Access
Reset Value
Section/Page
0x804
MAC Status Register (MACSR)
32
R/W
0x0000_0000
0x805
MAC Address Mask Register (MASK)
32
R/W
0xFFFF_FFFF
0x806
MAC Accumulator 0 (ACC0)
32
R/W
Undefined
0x807
MAC Accumulator 0,1 Extension Bytes (ACCext01)
32
R/W
Undefined
0x808
MAC Accumulator 2,3 Extension Bytes (ACCext23)
32
R/W
Undefined
0x809
MAC Accumulator 1 (ACC1)
32
R/W
Undefined
0x80A
MAC Accumulator 2 (ACC2)
32
R/W
Undefined
0x80B
MAC Accumulator 3 (ACC3)
32
R/W
Undefined
1
The values listed in this column represent the Rc field used when accessing the core registers via the BDM port. For more
information see
BDM: 0x804 (MACSR)
Access: Supervisor read/write
BDM read/write
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PAVn
OMC S/U
F/I
R/T
N
Z
V EV
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0
0
0
0
0
0
0
0
Figure 4-2. MAC Status Register (MACSR)
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order
from
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United
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International
Trade
Commission,
BGA-packaged
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part
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import
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sale
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prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
