UART Modules
26-28
Freescale Semiconductor
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
To configure the UART for DMA requests:
1. Initialize the DMAREQC in the SCM to map the desired UART DMA requests to the desired DMA
channels. For example, setting DMAREQC[7:4] to 1000 maps UART0 receive DMA requests to
DMA channel 1, setting DMAREQC[11:8] to 1101 maps UART1 transmit DMA requests to DMA
channel 2, and so on. It is possible to independently map transmit-based and receive-based UART
DMA requests in the DMAREQC.
2. Disable interrupts using the UIMR register. The appropriate UIMR bits must be cleared so that
interrupt requests are disabled for those conditions for which a DMA request is desired. For
example, to generate transmit DMA requests from UART1, UIMR1[TXRDY] should be cleared.
This prevents TXRDY from generating an interrupt request while a transmit DMA request is
generated.
3. Enable DMA access to the UART
n
registers by setting the corresponding PACR register in the
SCM for read/write in supervisor and user modes.
4. Enable DMA access to SRAM by setting the SPV bit in the core RAMBAR, and the BDE bit in
the SCM RAMBAR
5. Initialize the DMA channel. The DMA should be configured for cycle steal mode and a source and
destination size of one byte. This causes a single byte to be transferred for each UART DMA
request. Set the disable request bit (DCR
n
[D_REQ] to disable external requests when the BCR
reaches zero.
6. For a transmit process:
— Set the DMA SAR register to the address of the source data
— Set DCR
n
[SINC] to increment the source pointer
— Set DAR to the address if the UART transmit buffer (UTB)
— Clear DCR
n
[DINC]
— Set BCR to the number of bytes to transmit.
7. For a receive process:
— Set the DMA SAR register to the address of the UART receive buffer (URB)
— Clear DCR
n
[SINC]
— Set DAR to the address of the source data
— Set DCR
n
[DINC] to increment the destination pointer
— Set BCR to the number of bytes to transmit.
8. Start the data transfer by setting DCR
n
[EEXT], which enables the UART channel to issue DMA
requests.
shows the DMA requests.
Table 26-14. UART DMA Requests
Register
Bit
DMA Request
UISRn
1
Receive DMA request
UISRn
0
Transmit DMA request
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
