Debug Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
Freescale Semiconductor
31-3
31.3
Memory Map/Register Definition
In addition to the existing BDM commands that provide access to the processor’s registers and the memory
subsystem, the debug module contain a number of registers to support the required functionality. These
registers are also accessible from the processor’s supervisor programming model by executing the
WDEBUG instruction (write only). Therefore, the breakpoint hardware in debug module can be read or
written by the external development system using the debug serial interface
or written by the operating
system running on the processor core. Software guarantees that accesses to these resources are serialized
and logically consistent. Hardware provides a locking mechanism in CSR to allow external development
system to disable any attempted writes by the processor to the breakpoint registers (setting CSR[IPW]).
BDM commands must not be issued if the ColdFire processor is using the WDEBUG instruction to access
debug module registers, or the resulting behavior is undefined. The DSCLK must be quiescent during
operation of the WDEBUG command.
, are treated as 32-bit quantities, regardless of the number of
implemented bits. These registers are also accessed through the BDM port by the commands,
WDMREG
and
RDMREG
Section 31.4.1.5, “BDM Command Set”.
These commands contain a 5-bit field,
DRc, that specifies the register, as shown in
.
Processor Status
Clock (PSTCLK)
Delayed version of the processor clock. Its rising edge appears in the center of valid PST and DDATA
output. PSTCLK indicates when the development system should sample PST and DDATA values.
The following figure shows PSTCLK timing with respect to PSTD and DATA.
If real-time trace is not used, setting CSR[PCD] keeps PSTCLK, PST and DDATA outputs from
toggling without disabling triggers. Non-quiescent operation can be reenabled by clearing CSR[PCD],
although the external development systems must resynchronize with the PST and DDATA outputs.
PSTCLK starts clocking only when the first non-zero PST value (0xC, 0xD, or 0xF) occurs during
system reset exception processing.
describes PST values.
Debug Data
(DDATA[3:0])
These output signals display the register breakpoint status as a default, or optionally, captured
address and operand values. The capturing of data values is controlled by the setting of the CSR.
Additionally, execution of the WDDATA instruction by the processor captures operands that are
displayed on DDATA. These signals are updated each processor cycle. These signals are not
implemented on packages containing fewer than 100 pins.
Processor Status
(PST[3:0])
These output signals report the processor status.
shows the encoding of these signals.
These outputs indicate the current status of the processor pipeline and, as a result, are not related to
the current bus transfer. The PST value is updated each processor cycle. These signals are not
implemented on packages containing fewer than 100 pins.
All Processor Status
Outputs (ALLPST)
ALLPST is a logical AND of the four PST signals and is provided on all packages. PST[3:0] and
DDATA[3:0] are not available on the low cost (less than 100 pin) packages. When asserted, reflects
that the core is halted.
Table 31-2. Debug Module Signals (continued)
Signal
Description
PSTCLK
PST
or
DDATA
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
