General Purpose I/O Module
MCF52235 ColdFire® Integrated Microcontroller Reference Manual, Rev. 6
14-6
Freescale Semiconductor
14.6.2
Port Data Direction Registers (DDRn)
The DDR
n
registers control the direction of the port
n
pin drivers when the pins are configured for digital
I/O.
The DDRn registers with a full 8-bit implementation are shown in
n
registers use fewer than eight bits. Their bit definitions are shown in
, and
. The fields are described in
, which applies to all DDR
n
registers.
The DDR
n
registers are read/write. At reset, all bits in the DDR
n
registers are cleared to 0s.
Setting any bit in a DDR
n
register configures the corresponding port
n
pin as an output. Clearing any bit
in a DDR
n
register configures the corresponding pin as an input.
IPSBAR
Offsets:
0x10_000C (PORTQS)
0x10_0015 (PORTLD)
Access: User read/write
7
6
5
4
3
2
1
0
R
0
PORT
n
6
PORT
n
5
PORT
n
4
PORT
n
3
PORT
n
2
PORT
n
1
PORT
n
0
W
Reset:
0
1
1
1
1
1
1
1
Figure 14-4. Port Output Data Registers with Bits 6:0 Implemented (PORTQS, PORTLD)
IPSBAR
Offset: 0x10_0008 (PORTNQ)
Access: User read/write
7
6
5
4
3
2
1
0
R
PORT
n
7
PORT
n
6
PORT
n
5
PORT
n
4
PORT
n
3
PORT
n
2
PORT
n
1
0
W
Reset:
1
1
1
1
1
1
1
0
Figure 14-5. Port NQ Output Data Register (PORTNQ)
Table 14-2. PORTn Field Descriptions
Field
Description
Portnx
Data to be driven when the port pin is configured as a digital output.
1 Output is a logic 1
0 Output is a logic 0
Because
of
an
order
from
the
United
States
International
Trade
Commission,
BGA-packaged
product
lines
and
part
numbers
indicated
here
currently
are
not
available
from
Freescale
for
import
or
sale
in
the
United
States
prior
to
September
2010:MCF52234CVM60,
MCF52235CVM60
