Chapter 6. MPC8240 Memory Interface
6-17
SDRAM Interface Operation
After configuration of all parameters is complete, system software must set the
MCCR1[MEMGO] bit to enable the memory interface. The MPC8240 then conducts an
initialization sequence to prepare the SDRAM array for accesses. The initialization
sequence for JEDEC compliant SDRAM is as follows:
•
Precharge all internal banks of the SDRAM device.
•
Issue 8 refresh commands.
•
Issue mode register set command to initialize the mode register.
When the sequence completes, the SDRAM array is ready for access.
6.2.5 MPC8240 Interface Functionality for JEDEC SDRAMs
All read or write accesses to SDRAM are performed by the MPC8240 using various
combinations of the JEDEC standard SDRAM interface commands. SDRAM samples
command and data inputs on rising edges of the memory clock. Additionally, SDRAM
output data must be sampled on rising edges of the memory clock. Table 6-10 describes the
MPC8240 SDRAM interface command and data inputs.
The following SDRAM interface commands are provided by the MPC8240.
•
Bank Activate—Latches row address and initiates memory read of that row. Row
data is latched in SDRAM sense amplifiers and must be restored by a precharge
command before another bank activate is done.
•
Precharge—Restores data from the sense amplifiers to the appropriate row. Also
initializes the sense amplifiers in preparation for reading another row in the memory
array, (performing another activate command). Precharge must be performed if the
row address will change on next access.
•
Read—Latches column address and transfers data from the selected sense amplifier
to the output buffer as determined by the column address. During each succeeding
clock, additional data will be output without additional read commands. The amount
of data so transferred is determined by the burst size.
•
Write—Latches column address and transfers data from the data pins to the selected
sense amplifier as determined by the column address. During each succeeding clock,
additional data is transferred to the sense amplifiers from the data pins without
additional write commands. The amount of data so transferred is determined by the
burst size. Sub-burst write operations are controlled with DQM[0:7].
•
Refresh (similar to CAS before RAS)—Causes a row to be read in both memory
banks (JEDEC SDRAM) as determined by the refresh row address counter. This
refresh row address counter is internal to the SDRAM. After being read, the row is
automatically rewritten in the memory array. Before execution of refresh, all
memory banks must be in a precharged state.
Summary of Contents for MPC8240
Page 1: ...MPC8240UM D Rev 1 1 2001 MPC8240 Integrated Processor User s Manual ...
Page 38: ...xviii MPC8240 Integrated Processor User s Manual TABLES Table Number Title Page Number ...
Page 48: ...xlviii MPC8240 Integrated Processor User s Manual Acronyms and Abbreviations ...
Page 312: ...6 94 MPC8240 Integrated Processor User s Manual ROM Flash Interface Operation ...
Page 348: ...7 36 MPC8240 Integrated Processor User s Manual PCI Host and Agent Modes ...
Page 372: ...8 24 MPC8240 Integrated Processor User s Manual DMA Register Descriptions ...
Page 394: ...9 22 MPC8240 Integrated Processor User s Manual I2O Interface ...
Page 412: ...10 18 MPC8240 Integrated Processor User s Manual Programming Guidelines ...
Page 454: ...12 14 MPC8240 Integrated Processor User s Manual Internal Arbitration ...
Page 466: ...13 12 MPC8240 Integrated Processor User s Manual Exception Latencies ...
Page 516: ...16 14 Watchpoint Trigger Applications ...
Page 538: ...B 16 MPC8240 Integrated Processor User s Manual Setting the Endian Mode of Operation ...
Page 546: ...C 8 MPC8240 Integrated Processor User s Manual ...
Page 640: ...INDEX Index 16 MPC8240 Integrated Processor User s Manual ...