Glossary of Terms and Abbreviations
Glossary-3
Exclusive state. EMI state (E) in which only one caching device contains
data that is also in system memory.
Execution synchronization. All instructions in execution are architecturally
complete before beginning execution (appearing to begin execution)
of the next instruction. Similar to context synchronization but doesn't
force the contents of the instruction buffers to be deleted and
refetched.
Flush. An operation that causes a modified cache block to be invalidated and
the data to be written to memory.
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Instruction queue. A holding place for instructions fetched from the current
instruction stream.
Integer unit. The functional unit in the 603e responsible for executing all
integer instructions.
Interrupt. An external signal that causes the 603e to suspend current
execution and take a predefined exception.
Invalid state. EMI state (I) that indicates that the cache block does not
contain valid data.
Kill. An operation that causes a cache block to be invalidated.
Latency. The number of clock cycles necessary to execute an instruction and
make ready the results of that instruction.
Little-endian. A byte-ordering method in memory where the address n of a
word corresponds to the least significant byte. In an addressed
memory word, the bytes are ordered (left to right) 3, 2, 1, 0, with 3
being the most significant byte.
Low-drop-out.A term used to describe linear power supplies that supply a
stable output even when the V
in
-V
out
difference is low.
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Memory-mapped accesses. Accesses whose addresses use the segmented or
block address translation mechanisms provided by the MMU and
that occur externally with the bus protocol defined for memory.
Memory coherency. Refers to memory agreement between caches and
system memory (for example, EMI cache coherency).
F
I
K
L
M
Summary of Contents for MPC8240
Page 1: ...MPC8240UM D Rev 1 1 2001 MPC8240 Integrated Processor User s Manual ...
Page 38: ...xviii MPC8240 Integrated Processor User s Manual TABLES Table Number Title Page Number ...
Page 48: ...xlviii MPC8240 Integrated Processor User s Manual Acronyms and Abbreviations ...
Page 312: ...6 94 MPC8240 Integrated Processor User s Manual ROM Flash Interface Operation ...
Page 348: ...7 36 MPC8240 Integrated Processor User s Manual PCI Host and Agent Modes ...
Page 372: ...8 24 MPC8240 Integrated Processor User s Manual DMA Register Descriptions ...
Page 394: ...9 22 MPC8240 Integrated Processor User s Manual I2O Interface ...
Page 412: ...10 18 MPC8240 Integrated Processor User s Manual Programming Guidelines ...
Page 454: ...12 14 MPC8240 Integrated Processor User s Manual Internal Arbitration ...
Page 466: ...13 12 MPC8240 Integrated Processor User s Manual Exception Latencies ...
Page 516: ...16 14 Watchpoint Trigger Applications ...
Page 538: ...B 16 MPC8240 Integrated Processor User s Manual Setting the Endian Mode of Operation ...
Page 546: ...C 8 MPC8240 Integrated Processor User s Manual ...
Page 640: ...INDEX Index 16 MPC8240 Integrated Processor User s Manual ...