Chapter 11. Embedded Programmable Interrupt Controller (EPIC) Unit
11-15
Programming Guidelines
Depending on the interrupt system configuration, the EPIC unit may generate false
interrupts to clear out interrupts either latched during power-up or due to resetting the EPIC
unit. A spurious or real vector will be returned for an interrupt acknowledge cycle. See
programming note below for the cases that return a real interrupt vector for a false interrupt.
NOTE:
Edge-sensitive false interrupts—Because edge-sensitive
interrupts are not cleared until they are acknowledged and the
default polarity/sense bits for all interrupts are set to
edge-sensitive, it is possible for the EPIC unit to store
detections of edges at power-up as pending interrupts. If
software permanently sets the polarity/sense of an interrupt
source to edge-sensitive, it may receive the vector for the
interrupt source and not a spurious vector after software clears
the mask bit. This can occur once for any edge-sensitive
interrupt source when its mask is first cleared and the EPIC unit
is in mixed mode.
To prevent having to handle a false interrupt for this case,
software can clear the EPIC interrupt pending register of edges
detected during power-up by first setting the polarity/sense bits
of the interrupt source to level-sensitive as follows: high level
if the line is a positive-edge source, low level if the line is a
negative-edge source (and the mask bit should remain set).
Software can then set the interrupt source’s polarity/sense bits
to the appropriate values.
Global timer false interrupts—If the EPIC unit has been
initialized, the global timers were being used, and the EPIC
unit is reset by setting the GCR[R] bit, the following occurs:
If the EPIC unit is reset when a GTCCR[T] = 1, a false interrupt
is generated when that interrupt vector is unmasked after the
reset sequence completes. By following the recommended
initialization sequence in Steps 1–7 of this section during the
initialization of the EPIC unit, this false interrupt can be
handled without unexpected side effects. Unlike the above
edge-sensitive case of false interrupts, there is no method of
preventing having to handle this false interrupt.
Summary of Contents for MPC8240
Page 1: ...MPC8240UM D Rev 1 1 2001 MPC8240 Integrated Processor User s Manual ...
Page 38: ...xviii MPC8240 Integrated Processor User s Manual TABLES Table Number Title Page Number ...
Page 48: ...xlviii MPC8240 Integrated Processor User s Manual Acronyms and Abbreviations ...
Page 312: ...6 94 MPC8240 Integrated Processor User s Manual ROM Flash Interface Operation ...
Page 348: ...7 36 MPC8240 Integrated Processor User s Manual PCI Host and Agent Modes ...
Page 372: ...8 24 MPC8240 Integrated Processor User s Manual DMA Register Descriptions ...
Page 394: ...9 22 MPC8240 Integrated Processor User s Manual I2O Interface ...
Page 412: ...10 18 MPC8240 Integrated Processor User s Manual Programming Guidelines ...
Page 454: ...12 14 MPC8240 Integrated Processor User s Manual Internal Arbitration ...
Page 466: ...13 12 MPC8240 Integrated Processor User s Manual Exception Latencies ...
Page 516: ...16 14 Watchpoint Trigger Applications ...
Page 538: ...B 16 MPC8240 Integrated Processor User s Manual Setting the Endian Mode of Operation ...
Page 546: ...C 8 MPC8240 Integrated Processor User s Manual ...
Page 640: ...INDEX Index 16 MPC8240 Integrated Processor User s Manual ...