Copyright © Siemens AG 2016. All rights reserved
56
ERTEC 200P-2 Manual
Technical data subject to change
Version 1.0
In edge-triggered mode, each level on the input for synchronous signals must be sta-
ble for at least one clock, for asynchronous signals for at least two clocks.
In level-triggered mode, an active level must be present until the CPU confirms this
interrupt with an acknowledge.
-
When in level-triggered mode an interrupt is still active at the end of the processing
(acknowledge and EOI), a further interrupt will be output to the CPU as soon as
the corresponding bit in the ISREG has been cleared by the EOI command and no
higher-priority interrupt is present.
-
When in level-triggered mode an interrupt is removed by the source before the
CPU can confirm it with an acknowledge, however after the removal of the
interrupt the CPU nevertheless performs an acknowledge, the ICU returns the
default vector (null vector) as interrupt vector.
The edge (rising/falling) for which the ICU detects an interrupt on an input set to edge
triggering can be set separately for each interrupt input by setting the appropriate bit in
the EDGEREG register.
An interrupt detected at the input will be entered in the Interrupt-Request register. Provid-
ed it is not masked, after being entered, it will be led to the priority decoder. The entry will
be cleared when the corresponding interrupt is confirmed by the CPU with an
acknowledge and so will be entered in the In-Service register.
Each bit in the Interrupt Request register can be cleared using an appropriate command
issued in the IRCLVEC software register passing the number of the bit to be cleared. The
bit is cleared when a write access to IRCLVEC is detected.
Each interrupt can also be triggered other than using the appropriate ICU input signal by
setting the appropriate bit in the Software Interrupt registers
(SWIRREG/INTB_SWIRREG). After setting the bit, no minimum time must be observed
for the renewed clearing of the bit.
To allow several interrupts to be triggered simultaneously, the SWIRREG consists of
several 32-bit registers. A software interrupt is forwarded directly to the IRREG and then
handled like every other interrupt. The same procedure applies to the fast interrupts trig-
gered in the register INTB_SWIRREG. The following section discusses the software
interrupts depending on the trigger mode:
In level-triggered mode, the Interrupt Request register (INTA_IRREG or
INTB_IRREG) is affected directly by the INTA_SWIRREG or INTB_SWIRREG. Under
the prerequisite that no interrupt is present at the ICU input, a bit in the Software In-
terrupt register represents the corresponding bit in the Interrupt Request register.
In edge-triggered mode, a bit is set in the Interrupt Request register when the appro-
priate bit in the Software Interrupt register indicates a rising edge.
Warning:
There is a difference for the processing of software interrupts compared with normal
interrupt sources: when the software triggers an interrupt by setting the appropriate bit in
the Software Interrupt register, but clears it again with a clear command using the
IRCLVEC software register, the corresponding bit in the Interrupt Request register will be
inactive for only one clock and then becomes active again immediately, i.e. in interaction
of software interrupt and clear command – and only in this regard – the software interrupt
is always treated as level-triggered.
