User’s Manual U12697EJ3V0UM
CHAPTER 9 8-BIT TIMER/EVENT COUNTERS 1, 2
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9.4.5 Operation as interval timer (16-bit operation)
•
Cascade connection (16-bit timer) mode
By setting bit 4 (TMC24) of 8-bit timer mode control register 2 (TMC2) to 1, the timer enters the timer/counter
mode with 16-bit resolution.
With the count preset in 8-bit compare registers 10 and 20 (CR10, CR20) as the interval, the timer operates
as an interval timer by repeatedly generating interrupt requests.
<Setting method>
<1> Set each register.
•
PRM1: TM1 selects the count clock. TM2 connected in cascade are not used in setting.
•
CRn0: Compare values (Each compare value can be set from 00H to FFH.)
•
TMCn: Select the clear and start mode when TMn and CRn0 match.
TM1
→
TMC1 = 0000
×××
0B,
×
: don’t care
TM2
→
TMC2 = 0001
×××
0B,
×
: don’t care
<2> Setting TCE2 = 1 for TMC2 and finally setting TCE1 = 1 in TMC1 starts the count operation.
<3> If the values of TMn of all timers connected in cascade and CRn0 match, the INTTM1 of TM1 is generated.
(TM1 and TM2 are cleared to 00H.)
<4> INTTM1 are repeatedly generated at the same interval.
Cautions 1. Always set the compare register (CR10, CR20) after stopping timer operation.
2. If TM2 count matches CR20 even when used in a cascade connection, INTTM2 of TM2 is
generated. Always mask the high-order timer in order to disable interrupts.
3. The TCE1, TCE2 setting begins at TM2. Set theTM1 last.
4. Restarting and stopping the count is possible by setting only 1 or 0 in TCE1 of TMC1 to start
and stop it. Note, however, that the TCE1 bit of TMC1 and TCE2 bit of TMC2 must be cleared
when setting the compare register (CR10, CR20).
Figure 9-10 shows a timing example of the cascade connection mode with 16-bit resolution.
Figure 9-10. Cascade Connection Mode with 16-Bit Resolution
Count
clock
TM1
TM2
CR10
CR20
TCE1
TCE2
INTTM1
TO1
00H
00H
01H
N + 1
N
FFH 00H
FFH 00H
FFH 00H 01H
N 00H 01H
A 00H
N
M
01H
02H
M – 1 M
00H
B 00H
Operation enabled
Count starts
Interval time
Interrupt
request
generated
Level inverted
Counter cleared
Operation
stopped
