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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U12697EJ3V0UM
Example
The action of the overflow flag when an 8-bit addition instruction is executed is described next.
When 78H (+120) and 69H (+105) are added, the operation result becomes E1H (+225). Since the
upper limit of two’s complement is exceeded, the P/V flag is set to 1. In a two’s complement expression,
E1H becomes –31.
78H (+120) =
0111 1000
+) 69H (+105) = +) 0110 1001
0 1110 0001 = –31 P/V = 1
↑
CY
Next, since the operation result of the addition of the following two negative numbers falls within the
two’s complement range, the P/V flag is reset to 0.
FBH (–5)
=
1111 1011
+) F0H (–16)
= +) 1111 0000
1 1110 1011 = –21 P/V = 0
↑
CY
(3) Interrupt request enable flag (IE)
This flag controls the CPU interrupt request acceptance.
If IE is 0, interrupts are disabled, and only non-maskable interrupts and unmasked macro services can be
accepted. Otherwise, everything is disabled.
If IE is 1, the interrupt enable state is entered. Enabling the acceptance of interrupt requests is controlled by
the interrupt mask flags that correspond to each interrupt request and the priority of each interrupt.
This flag is set to 1 by executing the EI instruction and is reset to 0 by executing the DI instruction or by interrupt
acknowledgement.
(4) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow to bit 3, this flag is set to 1. Otherwise, the flag is reset
to 0.
This flag is used when the ADJBA and ADJBS instructions are executing.
