CHAPTER 16 ASYNCHRONOUS SERIAL INTERFACE/3-WIRE SERIAL I/O
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User’s Manual U12697EJ3V0UM
(1) Transmit shift registers 1, 2 (TXS1, TXS2)
These registers are used to set transmit data. Data written to TXS1 and TXS2 is sent as serial data.
If a data length of 7 bits is specified, bits 0 to 6 of the data written to TXS1 and TXS2 are transferred as transmit
data. Transmission is started by writing data to TXS1 and TXS2.
TX1 and TX2 can be written with an 8-bit memory manipulation instruction, but cannot be read.
RESET input sets TXS1 and TXS2 to FFH.
Caution
Do not write to TXS1 and TXS2 during transmission.
TXS1, TXS2 and receive buffer registers 1, 2 (RXB1, RXB2) are allocated to the same address.
Therefore, attempting to read TXS1 and TXS2 will result in reading the values of RXB1 and
RXB2.
(2) Receive shift registers 1, 2 (RX1, RX2)
These registers are used to convert serial data input to the R
X
D1 and R
X
D2 pins to parallel data. Receive data
is transferred to receive buffer register 1, 2 (RXB1, RSB2) one byte at a time as it is received.
RX1 and RX2 cannot be directly manipulated by program.
(3) Receive buffer registers 1, 2 (RXB1, RXB2)
These registers are used to hold receive data. Each time one byte of data is received, new receive data is
transferred from receive shift registers 1, 2 (RX1, RX2)
If a data length of 7 bits is specified, receive data is transferred to bits 0 to 6 of RXB1 and RXB2, and the MSB
of RXB1 and RXB2 always becomes 0.
RXB1 and RXB2 can be read by an 8-bit memory manipulation instruction, but cannot be written.
RESET input sets RXB1 and RXB2 to FFH.
Caution
RXB1, RXB2 and transmit shift registers 1, 2 (TXB1, TXB2) are allocated to the same address.
Therefore, attempting to read RXB1 and RXB2 will result in reading the values of TXB1 and
TXB2.
(4) Transmission controller
This circuit controls transmit operations such as the addition of a start bit, parity bit, and stop bit(s) to data written
to transmit shift registers 1, 2 (TXS1, TXS2), according to contents set to asynchronous serial interface mode
registers 1, 2 (ASIM1, ASIM2).
(5) Reception controller
This circuit controls reception according to the contents set to asynchronous serial interface mode registers 1,
2 (ASIM1, ASIM2). It also performs error check for parity errors, etc., during reception and transmission. If it
detects an error, it sets a value corresponding to the nature of the error in asynchronous serial interface status
registers 1, 2 (ASIS1, ASIS2).
