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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U12697EJ3V0UM
Figure 3-6. Format of Program Status Word (PSW)
Symbol
7
6
5
4
3
2
1
0
PSWH
UF
RBS2
RBS1
RBS0
—
—
—
—
7
6
5
4
3
2
1
0
PSWL
S
Z
RSS
AC
IE
P/V
0
CY
Each flag is described below.
(1) Carry flag (CY)
This is the flag that stores the carry or borrow of an operation result.
When a shift rotate instruction is executed, the shifted out value is stored. When a bit manipulation instruction
is executed, this flag functions as the bit accumulator.
The CY flag state can be tested by a conditional branch instruction.
(2) Parity/overflow flag (P/V)
The P/V flag has the following two actions in accordance with the execution of the operation instruction.
The state of the P/V flag can be tested by a conditional branch instruction.
•
Parity flag action
The results of executing the logical instructions, shift rotate instructions, and CHKL and CHKLA instructions
are set to 1 when an even number of bits is set to 1. If the number of bits is odd, the result is reset to 0. However,
for 16-bit shift instructions, the parity flag from only the lower 8 bits of the operation result is valid.
•
Overflow flag action
The result of executing an arithmetic operation instruction is set to 1 only when the numerical range expressed
in two’s complement is exceeded. Otherwise, the result is reset to 0. Specifically, the result is the exclusive
or of the carry from the MSB and the carry to the MSB and becomes the flag contents. For example, in 8-
bit arithmetic operations, the two’s complement range is 80H (–128) to 7FH (+127). If the operation result
is outside this range, the flag is set to 1. If inside the range, it is reset to 0.
