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CHAPTER 23 LOCAL BUS INTERFACE FUNCTIONS
User’s Manual U12697EJ3V0UM
(2) Programmable wait control register 1 (PWC1)
PWC1 is an 8-bit register that sets the number of waits.
The insertion of wait cycles is controlled by PWC1 over the entire space.
PWC1 can be read and written by a 1-bit or 8-bit memory manipulation instruction.
RESET input sets PWC1 to AAH.
Figure 23-2. Format of Programmable Wait Control Register 1 (PWC1)
Address: 0FFC7H After reset: AAH R/W
Symbol
7
6
5
4
3
2
1
0
PWC1
×
×
×
×
×
×
PW01
PW00
PW01
PW00
Insertion wait cycles
Data access cycles,
fetch cycles
0
0
0
3
0
1
1
4
1
0
2
5
1
1
Low level period that is input
–
at the WAIT pin
Remarks 1.
The insertion of wait cycles is controlled by the entire address space (except for the peripheral
RAM area).
2.
×
: don’t care
(3) Programmable wait control register 2 (PWC2)
In the
µ
PD784225 Subseries, wait cycle insertion control can be performed for the entire address space in one
operation using the programmable wait control register 1 (PWC1). However, in the
µ
PD784225Y Subseries,
which incorporates an in-circuit emulator (ICE), the address space is partitioned, and wait control is performed
for each area separately (using both the PWC1 and PWC2 registers).
Consequently, when programmable debugging using the ICE in the
µ
PD784225Y Subseries, wait control must
be performed by setting both the PWC1 register and programmable wait control register 2 (PWC2). Set as shown
in Table 23-3 below. Note that the settings in PWC2 and PWC1 (except bits 1 and 0) are invalid in the
µ
PD784225
Subseries, and therefore have no negative effect.
Table 23-3. Settings of Program Wait Control Register 2 (PWC2)
Inserted Wait Cycle
µ
PD784225 Subseries
µ
PD784225Y Subseries
PWC1
PWC1
PWC2
0
×××× ××
00B
00H
0000H
1
×××× ××
01B
55H
5555H
2
×××× ××
10B
AAH
AAAAH
Low-level time input to WAIT pin
×××× ××
11B
FFH
FFFFH
