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CHAPTER 12 WATCHDOG TIMER
User’s Manual U12697EJ3V0UM
Figure 12-2. Format of Watchdog Timer Mode Register (WDM)
Address: 0FFC2H After reset: 00H R/W
Symbol
7
6
5
4
3
2
1
0
WDM
RUN
0
0
WDT4
0
WDT2
WDT1
0
RUN
Watchdog timer operation setting
0
Stops the watchdog timer.
1
Clears the watchdog timer and starts counting.
WDT4
Watchdog timer interrupt request priority
0
Watchdog timer interrupt request
<NMI pin input interrupt request
1
Watchdog timer interrupt request
>NMI pin input interrupt request
WDT2
WDT1
Count clock
Overflow time [ms]
(f
CLK
= 12.5 MHz)
0
0
f
CLK
/2
17
10.5
0
1
f
CLK
/2
19
41.9
1
0
f
CLK
/2
20
83.9
1
1
f
CLK
/2
21
167.8
Cautions 1. Only the special instruction (MOV WDM, #byte) can write to the watchdog timer mode register
(WDM).
2. When writing to WDM to set the RUN bit to 1, write the same value every time. Even if different
values are written, the contents written the first time cannot be updated.
3. When the RUN bit is set to 1, it cannot be reset to 0 by the software.
Remark
f
CLK
: Internal system clock (f
XX
to f
XX
/8)
f
XX
:
Main system clock oscillation frequency
