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CHAPTER 12 WATCHDOG TIMER
User’s Manual U12697EJ3V0UM
12.3 Operations
12.3.1 Count operation
The watchdog timer is cleared by setting the RUN bit of the watchdog timer mode register (WDM) to 1 to start
counting. After the RUN bit is set to 1, when the overflow time set by bits WDT2 and WDT1 in WDM has elapsed,
a non-maskable interrupt (INTWDT) is generated.
If the RUN bit is reset to 1 before the overflow time elapses, the watchdog timer is cleared, and counting restarts.
12.3.2 Interrupt priority order
The watchdog timer interrupt (INTWDT) can be specified as either maskable or non-maskable according to the
interrupt selection control register (SNMI) setting. When writing 0 to bit 1 (SWDT) of SNMI, the watchdog timer interrupt
can be used as a non-maskable interrupt. In addition to the INTWDT, the non-maskable interrupts include the interrupt
(NMI) from the NMI pin. By setting bit 4 of the watchdog timer mode register (WDM), the acceptance order when
INTWDT and NMI are simultaneously generated can be set.
If accepting NMI is given priority, even if INTWDT is generated in an NMI processing program that is executing,
INTWDT is not accepted, but is accepted after the NMI processing program ends.
