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CHAPTER 3 CPU ARCHITECTURE
User’s Manual U12697EJ3V0UM
3.8.2 Functions
In addition to being manipulatable in 8-bit units, general-purpose registers can be a pair of two 8-bit registers and
be manipulated in 16-bit units. Also four of the 16-bit registers can be combined with the 8-bit register for address
expansion and manipulated in 24-bit units.
Each register can generally be used as the temporary storage for the operation result or the operand of the operation
instruction between registers.
The area from 0FE80H to 0FEFFH (during LOCATION 0H instruction execution, or the 0FFE80H to 0FFEFFH
during LOCATION 0FH instruction execution) can be accessed by specifying an address as normal data memory
whether or not it is used as the general-purpose register area.
Since there are eight register banks in the 78K/IV Series, efficient programs can be written by suitably using the
register banks in normal processing or interrupt servicing.
Each register has the unique functions shown below.
A (R1):
•
This register is primarily for 8-bit data transfers and operation processing. It can be combined with all of the
addressing modes for 8-bit data.
•
This register can be used to store bit data.
•
This register can be used as a register that stores the offset value during indexed addressing or based indexed
addressing.
X (R0):
•
This register can store bit data.
AX (RP0):
•
This register is primarily for 16-bit data transfers and operation results. It can be combined with all of the
addressing modes for 16-bit data.
AXDE:
•
When a DIVUX, MACW, or MACSW instruction is executed, this register can be used to store 32-bit data.
B (R3):
•
This register functions as a loop counter and can be used by the DBNZ instruction.
•
This register can store the offset in indexed addressing and based indexed addressing.
•
This register is used as the data pointer in a MACW or MACSW instruction.
