CHAPTER 22 INTERRUPT FUNCTIONS
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User’s Manual U12697EJ3V0UM
22.9 When Interrupt Requests and Macro Service Are Temporarily Held Pending
When the following instructions are executed, interrupt acknowledgment and macro service processing is deferred
for 8 system clock cycles. However, software interrupts are not deferred.
EI
DI
BRK
BRKCS
RETCS
RETCSB !addr16
RETI
RETB
LOCATION 0H or LOCATION 0FH
POP PSW
POPU post
MOV PSWL, A
MOV PSWL, #byte
MOVG SP, # imm 24
Write instruction and bit manipulation instruction (excluding BT and BF) to interrupt control registers
Note
, MK0,
MK1 IMC, ISPR, and SNMI.
PSW bit manipulation instruction
(Excluding the BT PSWL.bit, $addr20 instruction, BF PSWL.bit, $addr20 instruction, BT PSWH.bit, $addr20
instruction, BF PSWH.bit, $addr20 instruction, SET1 CY instruction, NOT1 CY instruction, and CLR1 CY
instruction)
Note
Interrupt control registers: WDTIC, PIC0, PIC1, PIC2, PIC3, PIC4, PIC5, CSIIC0, SERIC1, SRIC1, STIC1,
SERIC2, SRIC2, STIC2, TMIC3, TMIC00, TMIC01, TMIC1, TMIC2, ADIC,
TMIC5, TMIC6, WTIC
Caution If problems are caused by a long pending period for interrupts and macro servicing when the
corresponding instructions are used in succession, a time at which interrupts and macro service
requests can be acknowledged should be provided by inserting an NOP instruction, etc., in the
series of instructions.
