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CHAPTER 18 I
2
C BUS MODE (
µ
PD784225Y SUBSERIES ONLY)
User’s Manual U12697EJ3V0UM
(1) Serial shift register 0 (IIC0)
The IIC0 register converts 8-bit serial data into 8-bit parallel data and 8-bit parallel data into 8-bit serial data. IIC0
is used in both transmission and reception.
The actual transmission and reception are controlled by writing and reading IIC0.
IIC0 is set by an 8-bit memory manipulation instruction.
RESET input sets IIC0 to 00H.
(2) Slave address register 0 (SVA0)
When used as a slave, this register sets a slave address.
SVA0 is set by an 8-bit memory manipulation instruction.
RESET input sets SVA0 to 00H.
(3) SO latch
The SO latch holds the output level of the SDA0 pin.
(4) Wake-up controller
This circuit generates an interrupt request when the address set in slave address register 0 (SVA0) and the
reception address matched, or when an extended code was received.
(5) Clock selector
This selects the sampling clock that is used.
(6) Serial clock counter
The serial clock that is output or input during transmission or reception is counted to check 8-bit data
communication.
(7) Interrupt request signal generator
This circuit controls the generation of the interrupt request signal (INTIIC0).
The I
2
C interrupt request is generated by the following two triggers.
•
Eighth or ninth clock of the serial clock (set by the WTIM0 bit
Note
)
•
Interrupt request is generated by detecting the stop condition (set by the SPIE0 bit
Note
)
Note
WTIM0 bit: Bit 3 in I
2
C bus control register 0 (IICC0)
SPIE0 bit:
Bit 4 in I
2
C bus control register 0 (IICC0)
(8) Serial clock controller
In the master mode, the clock output to pin SCL0 is generated by the sampling clock.
(9) Serial clock wait controller
This circuit controls the wait timing.
(10) Acknowledge output circuit, stop condition detector, start condition detector, acknowledge detector
These circuits output and detect the control signals.
(11) Data hold time correction circuit
This circuit generates the hold time of the data to the falling edge of the serial clock.