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CHAPTER 24 STANDBY FUNCTION
User’s Manual U12697EJ3V0UM
24.4 STOP Mode
24.4.1 Settings and operating states of STOP mode
The STOP mode is set by setting the STP bit in the standby control register (STBC) to one.
STBC can be written with 8-bit data by a special instruction. Therefore, the STOP mode is set by the MOV STBC,
#byte instruction.
When enable interrupts is set (IE flag in PSW is set to 1), specify three NOP instructions after the STOP mode
setting instruction (after the STOP mode is released). If this is not done, after the STOP mode is released, multiple
instructions can be executed before interrupts are accepted. Unfortunately, the order relationship between the
interrupt service and instruction execution changes. Since the problems caused by changes in the execution order
are prevented, the measures described earlier are required.
The system clock during setting can only be set to the main system clock.
Caution Since an interrupt request signal is used when releasing the standby mode, when an interrupt
source that sets the interrupt request flag or resets the interrupt mask flag is generated, even
though the stanby mode is entered, it is immediately released. When the STOP mode setting
instruction conflicts with the setting of an unmasked interrupt request flag or a non-maskable
interrupt request, either of following two statuses are entered.
(1) Status in which STOP mode is set once, and then released
(2) Status in which STOP mode is not set
The oscillation stabilization time after releasing STOP mode is inserted only for the status in
which STOP mode is set once and then released.
Next, the operating states during the STOP mode are described.
