CHAPTER 22 INTERRUPT FUNCTIONS
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User’s Manual U12697EJ3V0UM
(10) When the following instructions are executed, interrupt acknowledgement and macro service processing are held
pending for 8 system clocks. However, software interrupts are not held.
EI
DI
BRK
BRKCS
RETCS
RETCSB !addr16
RETI
RETB
LOCATION 0H or LOCATION 0FH
POP PSW
POPU post
MOV PSWL, A
MOV PSWL, #byte
MOVG SP, #imm24
Write instruction and bit manipulation instruction to interrupt control registers
Note
, MK0, MK1, IMC, ISPR, or
SNM1 register (excluding BT, BF instructions)
PSW bit manipulation instructions (excluding BT PSWL.bit, $addr20 instruction, BF PSWL.bit, $addr20
instruction, BT PSWH.bit, $addr20 instruction, BF PSWH.bit, $addr20 instruction, SET1 CY instruction,
NOT1 CY instruction, CLR1 CY instruction)
Note
Interrupt control registers: WDTIC, PIC0, PIC1, PIC2, PIC3, PIC4, PIC5, PIC6, CSIIC0, SERIC1, SRIC1,
STIC1, SERIC2, SRIC2, STIC2, TMIC3, TMIC00, TMIC01, TMIC1, TMIC2,
ADIC, TMIC5, TMIC6, TMIC7, TMIC8, WTIC, KRIC
Caution If problems are caused by a long pending period for interrupts and macro servicing when the
corresponding instructions are used in succession, a time at which interrupts and macro service
requests can be acknowledged should be provided by inserting an NOP instruction, etc., in the
series of instructions.
