Clock, Reset, and Power Control (CRP)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
5-27
Preliminary
On entry into SLEEP mode, if the NPC PCR LP_DBG bit is set, the CRP sets the NPC PCR
SLEEP_SYNC bit to inform the debug tool that SLEEP mode is being entered. The CRP waits for this bit
to be cleared before proceeding into SLEEP mode. During SLEEP mode, most of the SOC is powered
down, and the contents of the debug registers are lost. The CRP supports restoration of the debug registers
on wakeup from SLEEP mode. The CRP latches the NPC PCR LP_DBG bit upon entry into SLEEP mode.
On wakeup from SLEEP mode, if the latched bit is set, the CRP will place both the Z0 and Z1 cores into
debug mode. The CRP selects the 16 MHz IRC to clock the core debug logic, so the development tool does
not need to drive a clock on the TCK pin at this point. Once both cores have acknowledged that they have
entered debug mode, the CRP allows the TCK pin to drive the debug logic, enables the JTAG pins, release
the pad keepers for the Nexus pins, and drives the assertion of the TDO pin. The assertion of the TDO pin
indicates to the debug tool that it can now restore the debug register contents via the JTAG interface.
Although their pad keepers are released, the Nexus pins cannot be used until the NPC configuration is
restored. The TDO pin remains asserted until the debug tool sets the SLEEP_SYNC bit in the NPC PCR
register. At that point, TDO is negated, control of the pin given back to the JTAG controller, and the
wakeup interrupt is asserted to the Z0 and Z1 cores. A block diagram of the SOC blocks and the
connections between them to support debug on SLEEP wakeup is given in
.
Note that the CRP will only enable the debug pins that were enabled prior to SLEEP mode entry. For
example, if Nexus reduced port mode was enabled prior to SLEEP entry, then only the reduced port pins
will be enabled on the wakeup from SLEEP.
When SLEEP or STOP mode is entered from RUN mode with the pad keepers still enabled from a previous
SLEEP mode, the debug configuration is re-sampled and applied to the new low power mode. This
includes sampling the NPC PCR LP_DBG bit to determine if debug should be enabled in the low power
mode, and updating the Nexus pin configuration. However, if debug was not enabled when the pad keepers
were initially enabled, the CRP will not be able to assert the TDO pin to synchronize with the debug tool.
Therefore, the CRP does not support the sequence of entering SLEEP mode with debug disabled, and then
re-entering SLEEP/STOP with the pad keepers enabled, and debug enabled. In this case, the low power
mode will function as normal, but there is no capability for synchronization with the debug tool.
