Enhanced Direct Memory Access (eDMA)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
12-13
Preliminary
12.3.2.7
eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
The EDMA_SEEIR provides a memory-mapped mechanism to set a given bit in the EDMA_EEIRL to
enable the error interrupt for a given channel. The data value on a register write causes the corresponding
bit in the EDMA_EEIRL to be set. Setting bit 1 (SEEI[0]) provides a global set function, forcing the entire
contents of EDMA_EEIRL to be asserted. Reads of this register return all zeroes.
12.3.2.8
eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
The EDMA_CEEIR provides a memory-mapped mechanism to clear a given bit in the EDMA_EEIRL to
disable the error interrupt for a given channel. The data value on a register write causes the corresponding
bit in the EDMA_EEIRL to be cleared. Setting bit 1 (CEEI[0]) provides a global clear function, forcing
the entire contents of the EDMA_EEIRL to be zeroed, disabling error interrupts for all channels. Reads of
this register return all zeroes.
Table 12-8. EDMA_CERQR Field Descriptions
Field
Description
bit 0
Reserved.
CERQ[0:6]
Clear Enable Request.
0–15 Clear corresponding bit in EDMA_ERQRL
16–63 Reserved
64–127 Clear all bits in EDMA_ERQRL
Note: Bits 2 and 3(CERQR[1:2]) are not used.
Offset: EDM 0x001A
Access: User write only
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
SEEI[0:6]
Reset
0
0
0
0
0
0
0
0
Figure 12-8. eDMA Set Enable Error Interrupt Register (EDMA_SEEIR)
Table 12-9. EDMA_SEEIR Field Descriptions
Field
Description
bit 0
Reserved.
SEEI[0:6]
Set Enable Error Interrupt.
0–15 Set corresponding bit in EDMA_EIRRL
16–63 Reserved
64–127 Set all bits in EDMA_EEIRL
Note: Bits 2 and 3(SEEIRR[1:2]) are not used.
