Miscellaneous Control Module (MCM)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
16-10
Freescale Semiconductor
Preliminary
If both a flash and RAM non-correctable error occur at the same time, the MCM records the event with
the highest priority, RNCE, and finally FNCE.
16.2.2.5.3
ECC Error Generation Register (EEGR)
The ECC error generation register is a 16-bit control register used to force the generation of single- and
double-bit data inversions in the memories with ECC, most notably the RAM. This capability is provided
for two purposes:
•
It provides a software-controlled mechanism for injecting errors into the memories during data
writes to verify the integrity of the ECC logic.
•
It provides a mechanism to allow testing of the software service routines associated with memory
error logging.
The intent is to generate errors during data write cycles, such that subsequent reads of the corrupted
address locations generate ECC events, either single-bit corrections or double-bit noncorrectable errors
that are terminated with an error response.
for the ECC error generation register definition.
Offset: MCM_BAS 0x0047
Access: User read/write
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
RNCE
FNCE
W
w1c
w1c
Reset
0
0
0
0
0
0
0
0
Figure 16-6. ECC Status (ESR) Register
Table 16-7. ESR Field Descriptions
Field
Description
bits 0–5
Reserved.
RNCE
RAM Non-Correctable Error. The occurrence of a properly-enabled non-correctable RAM error generates a MCM
ECC interrupt request. The faulting address, attributes, and data are also captured in the REAR, RESR, REMR,
REAT, and REDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
0 No reportable non-correctable RAM error has been detected.
1 A reportable non-correctable RAM error has been detected.
FNCE
Flash Non-Correctable Error. The occurrence of a properly-enabled non-correctable flash error generates a MCM
ECC interrupt request. The faulting address, attributes and data are also captured in the FEAR, FEMR, FEAT,
and FEDR registers. To clear this interrupt flag, write a 1 to this bit. Writing a 0 has no effect.
0 No reportable non-correctable flash error has been detected.
1 A reportable non-correctable flash error has been detected.
Offset: MCM_BAS 0x004A
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
FRCNCI FR1NCI
0
ERRBIT
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 16-7. ECC Error Generation (EEGR) Register
