Enhanced Modular I/O Subsystem (eMIOS200)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
26-39
Preliminary
FLAG can be generated at B1 matches, when MODE[5] is cleared, or on either A1 or B1 matches when
MODE[5] is set. If subsequent matches occur on comparators A and B, the PWM pulses continue to be
generated, regardless of the state of the FLAG bit.
FORCMA and FORCMB bits allow the software to force the output flip-flop to the level corresponding
to a match on A1 or B1. The FLAG bit is not set by the FORCMA and FORCMB operations.
Some rules applicable to the OPWMB mode include:
•
B1 matches have precedence over A1 matches if they occur at the same time within the same
counter cycle
•
A1=0 match from cycle(n) has precedence over B1 match from cycle(n-1)
•
A1 matches are masked out if they occur after B1 match within the same cycle
•
Any value written to A2 or B2 on cycle(n) is loaded to A1 and B1 registers at the following cycle
boundary (assuming OUDIS[n] is not asserted). The new values will be used for A1 and B1
matches in cycle(n+1)
describes the operation of the OPWMB mode regarding A1 and B1 matches and the
transition of the channel output pin. In this example EDPOL is set to zero.
Figure 26-35. OPWMB Mode Matches and Flags
1
4
A1 Match Negedge
6
A1 Value 0x000004
A1 Match
Output Pin
Selected
Time
B1 Match Negedge
B1 Match
B1 Value 0x000006
Clock
Prescaler
A2 Value
0x000000
0x000000
A1 Match Posedge Detection
1
8
6
FLAG Bit Set
EDPOL = 0
A1 Match Negedge
B1 Match Negedge
A1 Match Posedge
Detection
Detection
Detection
Detection
Cycle n
Cycle n+1
Write to A2
Detection
Counter Bus
