Enhanced Queued Analog-to-Digital Converter (eQADC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
31-59
Preliminary
In general, received data is moved into RFIFOs as they become available.
When time-stamped results return from the on-chip ADC, the conversion result and the time stamp are
always moved to the RFIFOs in consecutive clock cycles in order to guarantee they are always stored in
consecutive RFIFO entries.
31.4.5
On-Chip ADC Configuration and Control
31.4.5.1
Enabling and Disabling the on-chip ADC
The on-chip ADC has an enable bit (ADC0_CR[ADC0_EN], see
Section 31.3.4.1, “ADC0 Control
”) which allows the enabling of the ADC only when necessary. When the enable bit
for an ADC is negated, the clock input to that ADC is stopped. The ADC is disabled out of reset -
ADC0_EN negated - to allow for their safe configuration. The ADC must only be configured when its
enable bit is negated. Once the enable bit of the ADC is asserted, clock input is started, and the bias
generator circuit is turned on. When the enable bits of the ADC is negated, the bias circuit generator is
stopped.
NOTE
Conversion commands sent to a disabled ADC are ignored by the ADC
control hardware.
NOTE
An 8ms wait time from VDDA power up to enabling ADC or exiting from
stop or sleep mode is required to pre-charge the external 100nf capacitor on
REFBYPC. This time must be guaranteed by crystal startup time plus reset
duration or the user. The ADC internal bias generator circuit will start up
after 10us upon VRH/VRL power up and produces a stable/required bias
current to the pre-charge circuit, but the current to the other analog circuits
are disabled until the ADC is enabled. As soon as the ADC is enabled, the
bias currents to other analog circuits will be ready.
NOTE
Because of previous design versions, the eQADC will always wait 120
ADC clocks before issuing the first conversion command following the
enabling the on-chip ADC, or the exiting of stop mode. There is an
independent counter checking for this delay Conversion commands can start
to be executed whenever the counter completes counting 120 ADC clocks.
31.4.5.2
ADC Clock and Conversion Speed
The clock input to the ADC is defined by setting the ADC0_CR[ADC0_CLK_PS](see
“ADC0 Control Register (ADC0_CR)
”) The ADC0_CLK_PS field selects the clock divide factor by
which the system clock will be divided as showed in
. The ADC clock frequency is calculated
as below and it must not exceed 12 MHz.
