System Integration Unit (SIU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
6-42
Freescale Semiconductor
Preliminary
6.3.2.31
Parallel GPIO Pin Data Output Register 3 (SIU_PGPDO3)
The SIU_PGPDO3 register contains the parallel GPIO pin data output for PG0:PG15 and PH0:PH15.
Reads and writes to this register are coherent with the registers SIU_GPDO96_99, SIU_GPDO100_103,
SIU_GPDO104_107, SIU_GPDO108_111, SIU_GPDO112_115, SIU_GPDO116_119,
SIU_GPDO120_123, and SIU_GPDO124_127.
6.3.2.32
Parallel GPIO Pin Data Output Register 4 (SIU_PGPDO4)
The SIU_PGPDO4 register contains the parallel GPIO pin data output for PJ0:PJ15.
Reads and writes to this register are coherent with the registers SIU_GPDO18_131, SIU_GPDO132_135,
SIU_GPDO136_139, and SIU_GPDO140_143.
NOTE
On MPC5510, the port K pins are only inputs. Therefore, there are no
parallel GPIO pin data output bits associated with port K.
Offset
SI 0x0C08
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PE0:PE15
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PF0:PF15
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-33. Parallel GPIO Pin Data Output Register 2 (SIU_PGPDO2)
Offset:
SI 0x0C0C
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
PG0:PG15
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
PH0:PH15
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-34. Parallel GPIO Pin Data Output Register 3 (SIU_PGPDO3)
