External Bus Interface (EBI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
29-44
Freescale Semiconductor
Preliminary
shows an example of the termination signals protocol for back-to-back reads to two different
slave devices that properly take turns driving the termination signals. This assumes a system using slave
devices that drive termination signals.
Figure 29-31. Termination Signals Protocol Timing Diagram
29.4.2.10 Non-Chip-Select Burst in 16-bit Data Bus Mode
The timing diagrams in this section apply to the special case of a non-chip select 32-bit access in 16-bit
data bus mode. They specify the behavior for the EBI-master and EBI-slave, as the external master is
expected to be another MCU with this EBI.
For this case, a special 2-beat burst protocol is used for reads and writes, so the EBI-slave can internally
generate one 32-bit read or write access (thus 32-bit coherent), as opposed to two separate 16-bit accesses.
shows a 32-bit non-chip-select read in 16-bit data bus mode.
shows a 32-bit non-chip-select write in 16-bit data bus mode.
1
Latched version (1 cycle delayed) used for externally driven
TEA and TA.
T
he EBI drives address and control signals an extra cycle because it uses a latched version of TA
*
Th
is is the earliest that the EBI can start another transfer when continuing a set of small accesses.
For all other cases, an extra cycle is needed before the EBI can start another TS.
**
CLKOUT
BB
TS
DATA[0:31]
TA, TEA
ADDR[8:31]
RD_WR
Slave 1
Slave 2
*
*
**
(1 cycle delayed) to terminate the cycle. An external master is not required to do this.
Slave 1
negates
acknowledge
signals and
turns off
Slave 2
negates
acknowledge
signals and
turns off
Slave 2
allowed to
drive
acknowledge
signals
Slave 1
allowed to
drive
acknowledge
signals
