Deserial Serial Peripheral Interface (DSPI)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
23-46
Freescale Semiconductor
Preliminary
23.4.7.4
Delay after Transfer (t
DT
)
The delay after transfer is the length of time between negation of the PCS
x
signal for a frame and the
assertion of the PCS
x
signal for the next frame. See
for an illustration of the delay after
transfer. The PDT and DT fields in the DSPI
x
_CTAR
n
registers select the delay after transfer. The
following formula expresses the PDT/DT/delay after transfer relationship:
shows an example of the computed delay after transfer.
23.4.7.5
Peripheral Chip Select Strobe Enable (PCSS)
The PCSS signal provides a delay to allow the PCS
x
signals to settle after transitioning thereby avoiding
glitches. When the DSPI is in master mode and PCSSE bit is set in the DSPI
x
_MCR, PCSS provides a
signal for an external demultiplexer to decode the PCS
x
[0:4] signals into as many as 32 glitch-free PCS
x
signals.
shows the timing of the PCSS signal relative to PCS signals.
Figure 23-29. Peripheral Chip Select Strobe Timing
The delay between the assertion of the PCS
x
signals and the assertion of PCSS is selected by the PCSSCK
field in the DSPI
x
_CTAR based on the following formula:
At the end of the transfer the delay between PCSS negation and PCS
x
negation is selected by the PASC
field in the DSPI
x
_CTAR based on the following formula:
Table 23-24. After SCK Delay Computation Example
PASC
Prescaler
Value
ASC
Scaler
Value
Fsys
After SCK Delay
0b01
3
0b0100
32
66 MHz
1.44
μ
s
Table 23-25. Delay after Transfer Computation Example
PDT
Prescaler
Value
DT
Scaler
Value
f
SYS
Delay after Transfer
0b01
3
0b1110
32768
66 Hz
1.47 ms
t
DT
=
f
SYS
DT
×
PDT
1
×
PCSS
PCSx
t
PCSSCK
t
PASC
tPCSSCK =
PCSSCK
×
f
SYS
1
