MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
7-1
Preliminary
Chapter 7
Reset
7.1
Introduction
The reset sources supported in the MPC5510 are:
•
Power-on reset (POR)
•
Low-voltage inhibit (LVI) reset
•
External reset
•
Loss-of-lock reset
•
Loss-of-clock reset
•
Watchdog timer
•
JTAG reset
•
Checkstop reset (both Z1 and Z0 cores)
•
Software-system reset
All reset sources are processed by the reset controller, which is located in the SIU module (
“System Integration Unit (SIU)
”). The reset controller monitors the reset input sources and, upon detection
of a reset event, resets internal logic and controls the assertion of the RESET pin.
The MCU is clocked by the 16 MHz IRC clock after any reset.
The reset status register (SIU_RSR) gives the source, or sources, of the last reset and is updated for all reset
sources except JTAG reset
The BOOTCFG pin controls the MCU boot sequence after the POR or if the Z1 reset vector points to the
BAM. If the pin is driven low during the MCU reset, the MCU boots from internal flash and the Reset
Configuration Halfword (RCHW) controls the boot sequence. The RCHW needs to be programmed by
user in internal flash in one of predefined locations together with the user application start address.
If the pin is driven high, the BAM executes serial boot sequence.
Chapter 32, “Boot Assist Module (BAM)
for more details about the boot procedures.
7.2
External Signal Description.
Refer to
Section 2.7, “Detailed External Signal Descriptions
,” for signal properties.
