Interrupt Controller (INTC)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
9-5
Preliminary
last pushed PRI value would need to be popped simultaneously. In this case, PRI in the associated
INTC_CPR_PRC
n
is updated with the new priority, and the associated LIFO is neither pushed or popped.
9.1.3.2
Debug Mode
The INTC operation in debug mode is identical to its operation in normal mode.
9.1.3.3
Stop Mode
The INTC supports stop mode. The INTC can have its clock input disabled at any time by the clock driver
on the device. While its clocks are disabled, the INTC registers are not accessible.
The INTC requires clocking in order for a peripheral interrupt request to generate an interrupt request to
the processor. Since the INTC is not clocked in stop mode, peripheral interrupt requests can not be used as
a wakeup source, unless the clock, reset, and power module (CRP) supports that interrupt request as a
wakeup source.
9.2
Signal Description
The INTC has no external signals.
9.3
Memory Map and Registers
9.3.1
Module Memory Map
shows the INTC memory map.
Table 9-1. INTC Memory Map
Offset from
INTC_BASE_ADDR
(0xFFF4_8000)
Register
Access
Reset
Value
Section/Page
0x0000
INTC_MCR—INTC module configuration register
R/W
0x0000_0000
0x0004
Reserved
—
—
—
0x0008
INTC_CPR_PRC0—INTC current priority register for
processor 0 (Z1)
R/W
0x0000_000F
0x00C
INTC_CPR_PRC1—INTC current priority register for
processor 1 (Z0)
R/W
0x0000_000F
0x0010
INTC_IACKR_PRC0—INTC interrupt acknowledge register
for processor 0 (Z1)
R
1
/W
0x0000_0000
0x0014
INTC_IACKR_PRC1—INTC interrupt acknowledge register
for processor 1 (Z0)
R
1
/W
0x0000_0000
0x0018
INTC_EOIR_PRC0—INTC end of interrupt register for
processor 0 (Z1)
W
0x0000_0000
0x001C
INTC_EOIR_PRC1—INTC end of interrupt register for
processor 1 (Z0)
W
0x0000_0000
