e200z1 Core (Z1)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
Freescale Semiconductor
10-3
Preliminary
The condition register unit supports the condition register (CR) and condition register operations defined
by the Power Architecture. The condition register consists of eight 4-bit fields that reflect the results of
certain operations, such as move, integer and floating-point compare, arithmetic, and logical instructions,
and provide a mechanism for testing and branching.
Vectored and autovectored interrupts are supported by the CPU. Vectored interrupt support is provided to
allow multiple interrupt sources to have unique interrupt handlers invoked with no software overhead.
Figure 10-1. e200z1 Block Diagram
10.2.1
Instruction
Unit Features
The features of the e200 instruction unit are:
CPU
control logic
Load/
Data
Memory
management
unit
Address
store
unit
Instruction unit
Branch
unit
PC
Unit
Instruction buffer
GPR
CR
SPR
Multiply
unit
Data bus interface unit
Control
32
32
N
OnCE/Nexus
control logic
interface
Control
Data
(mtspr/mfspr)
Integer
execution
unit
External
SPR
CTR
XER
LR
Data
Address
Instruction bus interface unit
Control
32
64
N
