Controller Area Network (FlexCAN)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
25-28
Freescale Semiconductor
Preliminary
on a per message buffer basis. When the FIFO is enabled (FEN bit in CANx_MCR is set), the first eight
mask registers apply to the eight elements of the FIFO filter table (on a one-to-one correspondence), while
the rest of the registers apply to the regular MBs, starting from MB8.
The individual Rx mask registers are implemented in RAM, so they are not affected by reset and must be
explicitly initialized prior to any reception. Furthermore, they can only be accessed by the CPU while the
module is in freeze mode. Out of freeze mode, write accesses are blocked and read accesses will return
“all zeros”. Furthermore, if the BCC bit in the register is negated, any read or write operation to these
registers results in access error.
25.4
Functional Description
The FlexCAN module is a CAN protocol engine with a very flexible mailbox system for transmitting and
receiving CAN frames. The mailbox system is composed by a set of up to 64 message buffers (MB) that
store configuration and control data, time stamp, message ID and data (see
”). The memory corresponding to the first eight MBs can be configured to support a FIFO
reception scheme with a powerful ID filtering mechanism, capable of checking incoming frames against
a table of IDs (up to eight extended IDs or 16 standard IDs or 32 8-bit ID slices), each one with its own
individual mask register. Simultaneous reception through FIFO and mailbox is supported. For mailbox
reception, a matching algorithm makes it possible to store received frames only into MBs that have the
same ID programmed on its ID field. A masking scheme makes it possible to match the ID programmed
on the MB with a range of IDs on received CAN frames. For transmission, an arbitration algorithm decides
the prioritization of MBs to be transmitted based on the message ID (optionally augmented by 3 local
priority bits) or the MB ordering.
Offset: Base + 0880 - 0x0975
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
MI31
MI30
MI29
MI28
MI27
MI26
MI25
MI24
MI23
MI22
MI21
MI20
MI19
MI18
MI17
MI16
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
MI15
MI14
MI13
MI12
MI11
MI10
MI9
MI8
MI7
MI6
MI5
MI4
MI3
MI2
MI1
MI0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 25-15. Rx Individual Mask Registers (CANx_RXIMR0-CANx_RXIMR63)
Table 25-16. CANx_RXIMR0-CANx_RXIMR63 Field Descriptions
Field
Description
MI31–M0
Mask Bits
For normal Rx MBs, the mask bits affect the ID filter programmed on the MB. For the Rx FIFO, the mask bits
affect all bits programmed in the filter table (ID, IDE, RTR).
0 The corresponding bit in the filter is “don’t care”
1 The corresponding bit in the filter is checked against the one received
