System Integration Unit (SIU)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
6-4
Freescale Semiconductor
Preliminary
6.2
External Signal Description
Refer to
Section 2.7, “Detailed External Signal Descriptions
,” for signal properties.
6.2.1
Detailed Signal Descriptions
6.2.1.1
Reset (RESET)
To reset all MCU modules, an external device asserts the RESET pin. The RESET pin is also an
open-drain-output signal asserted during an internal reset. Assertion of the RESET pin when the device is
in reset restarts the reset cycle (see
6.2.1.2
General-Purpose I/O Pins
The GPIO pins provide general-purpose input and output function. The GPIO pins are generally
multiplexed with other I/O pin functions. An input (SIU_GPDI) or output (SIU_GPDO) register controls
each GPIO input and output separately. See
Section 6.3.2.14, “GPIO Pin Data Output Registers
(SIU_GPDO16_19–SIU_GPDO140_143)
Section 6.3.2.15, “GPIO Pin Data Input Registers
Section 6.3.2.28, “Parallel GPIO Pin Data Output Register 0
Section 6.3.2.37, “Parallel GPIO Pin Data Input Register 4 (SIU_PGPDI4)
Section 6.3.2.38, “Masked Parallel GPIO Pin Data Output Registers
6.2.1.3
Boot Configuration Pin (PD[2])
PD[2] is a GPIO pin. CNRX_B is the receive pin for the FlexCAN B module. eMIOS[10] is an
input/output channel pin for the eMIOS200 module. The BOOTCFG pin is sampled before the negation
of the RESET pin. The BAM program uses the value to determine the boot configuration.
6.2.1.4
Core Non Maskable Interrupt Pins (PD10 and PD11)
PD[10] is a GPIO pin. NMI0 is the critical interrupt input for the e200z1 core.
PD[11] is a GPIO pin. NMI1 is the critical interrupt input for the e200z0 core.
