Media Local Bus (MLB)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
33-4
Freescale Semiconductor
Preliminary
In each configuration, the MLB interface signals can be routed out in multiple pin positions on the
MPC551xE/G. The selection is made via the associated SIU_PCR[PA] field for the particular pin. See
for specific details.
NOTE
Port E and Port F are used to support the MLB signals. For timing reasons,
the MLB signals should not be mixed between the two ports at the same
time.
33.3
Memory Map and Registers
The SoftMLB Interface Logic memory map is shown in
. The address of each register is given
as an offset to the MLB base address. Registers are listed in address order, identified by complete name
and mnemonic, and show the type of access allowed. The memory map consists of a block of 64 address
locations which are aliased within the 16K block reserved for the MLB starting at the MLB_BASE
address.
Table 33-2. MLB Memory Map
Offset from
MLB_BASE
(0xFFF8_4000)
Register
Access
Reset Value
Section/Page
General Registers
0x00
MLB_MCR – Module Configuration Register
R/W
0x8000_0000
0x04
MLB_MBR – MLB Blank Register
R/W
0x0000_0000
0x08
MLB_MSR – Module Status Register
R
0x0000_0000
0x0C
MLB_RXCCHAR – RX Control Channel Address Register
R/W
0x0000_0000
0x10
MLB_RXACHAR – RX Async Channel Address Register
R/W
0x0000_0000
0x14
MLB_TXCCHAR – TX Control Channel Address Register
R/W
0x0000_0000
0x18
MLB_TXACHAR – TX Async Channel Address Register
R/W
0x0000_0000
0x1C
MLB_TXSCHAR – TX Sync Channel Address Register
R/W
0x0000_0000
0x20
MLB_TXSCHAMR – TX Sync Channel Address Mask Register
R/W
0x0000_003E
0x24
MLB_CLKACR – MLBCLK Clock Adjust Control Register
R/W
0x0000_0000
0x28
MLB_RXICHAR – RX Isochronous Channel Address Register
R/W
0x0000_0000
0x2C
MLB_TXICHAR – TX Isochronous Channel Address Register
R/W
0x0000_0000
Note: Unimplemented locations always read 0. Writes to unimplemented locations have no effect.
