Enhanced Direct Memory Access (eDMA)
MPC5510 Microcontroller Family Reference Manual, Rev. 1
12-14
Freescale Semiconductor
Preliminary
12.3.2.9
eDMA Clear Interrupt Request Register (EDMA_CIRQR)
The EDMA_CIRQR provides a memory-mapped mechanism to clear a given bit in the EDMA_IRQRL to
disable the interrupt request for a given channel. The given value on a register write causes the
corresponding bit in the EDMA_IRQRL to be cleared. Setting bit 1 (CINT[0]) provides a global clear
function, forcing the entire contents of the EDMA_IRQRL to be zeroed, disabling all eDMA interrupt
requests. Reads of this register return all zeroes.
Offset: EDM 0x001B
Access: User write only
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
CEEI[0:6]
Reset
0
0
0
0
0
0
0
0
Figure 12-9. eDMA Clear Enable Error Interrupt Register (EDMA_CEEIR)
Table 12-10. EDMA_CEEIR Field Descriptions
Field
Description
bit 0
Reserved.
CEEI[0:6]
Clear Enable Error Interrupt.
0–15 Clear corresponding bit in EDMA_EEIRL
16–63 Reserved
64–127 Clear all bits in EDMA_EEIRL
Note: Bits 2 and 3(CEEIR[1:2]) are not used.
Offset: EDM 0X001C
Access: User write only
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
CINT[0:6]
Reset
0
0
0
0
0
0
0
0
Figure 12-10. eDMA Clear Interrupt Request (EDMA_CIRQR)
Table 12-11. EDMA_CIRQR Field Descriptions
Field
Description
bit 0
Reserved.
CINT[0:6]
Clear Interrupt Request.
0–15 Clear corresponding bit in EDMA_IRQRL
16–63 Reserved
64–127 Clear all bits in EDMA_IRQRL
Note: Bits 2 and 3(CIRQR[1:2]) are not used.
